SH7147 Datasheet, PDF (197/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Origin of
Activation
Source
DTC Vector
Activation Vector Address
Source Number Offset
DTCE*¹
Transfer
Source
Transfer
Destination Priority
Synchronous SSRXI
233
serial
communication _SSTXI
234
unit
H'7A4
H'7A8
DTCERE7 SSRDR0 to
SSRDR3
DTCERE6 Any location*²
Any location*² High
SSTDR0 to
SSTDR3
RCAN-ET_0 RM0_0 242
H'7C8
DTCERE3
CONTROL0H Any location*²
to
CONTROL1L*³
RCAN-ET_1*⁴ RM0_1
246
H'7D8
DTCERE2
CONTROL0H Any location*²
to
CONTROL1L*³
Low
Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0. To leave software standby mode with an interrupt, write 0 to the
corresponding DTCE bit.
2. An external memory, a memory-mapped external device, an on-chip memory, or an on-
chip peripheral module (except for DTC, BSC, UBC, AUD, and FLASH) can be selected
as the source or destination. Note that at least either the source or destination must be
an on-chip peripheral module; transfer cannot be done among an external memory, a
memory-mapped external device, and an on-chip memory.
3. Read to a message control field in mailbox 0 by using a block transfer mode or etc.
4. Available only in the SH7142.
Rev. 3.00 Oct. 06, 2008 Page 173 of 1080
REJ09B0230-0300