SH7147 Datasheet, PDF (747/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
17.4.3 Message Transmission Sequence
• Message Transmission Request
The following sequence is an example to transmit a CAN frame onto the bus. As described in
the previous register section, please note that IRR8 is set when one of the TXACK or ABACK
bits is set, meaning one of the Mailboxes has completed its transmission or transmission
abortion and is now ready to be updated for the next transmission, whereas, the GSR2 means
that there is currently no transmission request made (No TXPR flags set).
RCAN-ET is in Tx_Rx Mode
(MBC[x] = 0)
Mailbox[x] is ready
to be updated for
next transmission
Update Message Data of
Mailbox[x]
Write '1' to the TXPR[x] bit
at any desired time
Clear TXACK[x]
Yes
No
TXACK[x] = 1?
Waiting for interrupt
Internal Arbitration
No
'x' Highest Priority?
Yes
Yes
IRR8 = 1?
No
Waiting for interrupt
Transmission Start
CAN Bus
Arbitration
Acknowledge Bit
CAN Bus
Figure 17.10 Transmission Request
Rev. 3.00 Oct. 06, 2008 Page 723 of 1080
REJ09B0230-0300