SH7147 Datasheet, PDF (968/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
Figure 23.8 shows an example in which more than one trace data are lost from two branch trace
events to be output. Figure 23.9 is an example where STDBY comes after the LOST command.
AUDCK
AUDSYNC
LOST command forcibly drives AUDSYNC to low
AUDATA[3:0]
BPC 0100
DA
3-0
DA
7-4
SA
3-0
PID
2-0
LOST BPC
0001
DA
3-0
SA
3-0
SA
7-4
PID
2-0
CMD1 CMD1
Branch
Branch PID CMD1 CMD1 CMD2 Branch
Branch
PID
destination
source
destination
source
address
address
address
address
Figure 23.8 Example of Failure to Get Trace Data during Real-time Trace
AUDCK
AUDSYNC
AUDATA[3:0]
LOST STDBY
CMD1 CMD1 CMD1
Figure 23.9 Example where STDBY Comes after the LOST Command
(6) Full Trace Mode
In full trace mode, all trace data is output outside without fail. Full trace mode can be selected by
setting the TM bit in AUCSR to 0. Trace data generated in full trace mode is output outside
through the internal FIFO in AUD. When FIFO becomes full, the CPU stops operation until FIFO
outputs its data.
In this case, unlike the real-time trace mode, trace data is not lost. When the CPU temporarily
stops operating because FIFO is full, the LOST command provides notification that the CPU has
temporarily stopped. However, AUDSYNC is always driven to L in the next cycle after the LOST
command in the same manner as for real-time trace.
Rev. 3.00 Oct. 06, 2008 Page 944 of 1080
REJ09B0230-0300