SH7147 Datasheet, PDF (54/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
Table 2.9 Instruction Formats
Instruction Format
0 type
15
0
xxxx xxxx xxxx xxxx
n type
15
0
xxxx nnnn xxxx xxxx
m type
15
0
xxxx mmmm xxxx xxxx
Source Operand
⎯
Destination
Operand
⎯
Sample Instruction
NOP
⎯
nnnn: register
MOVT Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register
direct
Control register or LDC Rm,SR
system register
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register
⎯
indirect
JMP @Rm
PC relative using ⎯
Rm
BRAF Rm
Rev. 3.00 Oct. 06, 2008 Page 30 of 1080
REJ09B0230-0300