SH7147 Datasheet, PDF (257/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Iφ
L bus
Bφ
I bus
Pφ
Periipheral
bus
(3 + n) × Iφ
(1 + m) × Bφ
2 × Pφ
2 × Iφ
Figure 9.13 Timing of Read Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:1
Rev. 3.00 Oct. 06, 2008 Page 233 of 1080
REJ09B0230-0300