SH7147 Datasheet, PDF (621/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.3.1 SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit: 7
6
5
4
3
2
1
0
MSS BIDE
-
SOL SOLP -
CSS[1:0]
Initial value: 0
0
0
0
1
1
0
1
R/W: R/W R/W R R/W R/W R R/W R/W
Initial
Bit
Bit Name Value R/W
7
MSS
0
R/W
6
BIDE
0
R/W
5
⎯
0
R
Description
Master/Slave Device Select
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
14.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
output)
1: Bidirectional mode (one pin is used for data input and
output)
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 597 of 1080
REJ09B0230-0300