SH7147 Datasheet, PDF (971/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
1. WD address 1 and PFDA undergo comparison matching at CMP1 and the lower bits of WD
address 1 are output (4/8/16/32 bits) according to the comparison result. The entire 32-bit WD
data 1 is then output and PDFA is renewed to WD address 1.
2. BR destination 1 and PFBA undergo comparison matching at CMP1, and BR source 1 and
PFBA undergo comparison matching at CMP2. The lower bits of BR destination 1 are then
output (4/8/16/32 bits) according to the comparison result at CMP1. The lower bits of BR
source 1 are also output (4/8/16/32 bits) according to the comparison result at CMP2. After
that, PFBA is renewed to BR destination 1.
3. BR destination 2 and PFBA undergo comparison matching at CMP1, and BR source 2 and
PFBA undergo comparison matching at CMP2. PFBA retains the value of BR destination 1 as
stored in step (2). The lower bits of BR destination 2 are then output (4/8/16/32 bits) according
to the comparison result at CMP1. The lower bits of BR source 2 are also output (4/8/16/32
bits) according to the comparison result at CMP2. After that, PFBA is renewed to BR
destination 2.
4. WD address 2 and PFDA undergo comparison matching at CMP1. PFDA retains the value of
WD address 1 stored in step (1). The lower bits of WD address 2 are output (4/8/16/32 bits)
according to the comparison result. An 8-bit WD data 1 is then output as it is and PDFA is
renewed to WD address 2.
5. When the output counter overflows, PFBA and PFDA are disabled. At the same time, the
branch destination, branch source, and data address part in the trace data are always output in
32-bit length.
23.3.9 Usage Notes (Branch Trace Mode)
(1) Guidelines for Initialization of Branch Trace Mode
The buffer in this debugger and the processing status are initialized under the following
conditions.
• Power-on reset
• Manual reset
• Hardware standby
• Low level is input to the AUDRST pin
• Software reset (when the AUDSRST bit in STBCR6 is cleared to 0)
• The EN bit in AUCSR is changed from 0 to 1
FIFO in the AUD is cleared.
Rev. 3.00 Oct. 06, 2008 Page 947 of 1080
REJ09B0230-0300