SH7147 Datasheet, PDF (974/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 23.12).
If a command other than the above is input in DIR, the AUD treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the
Ready flag to 1 (figure 23.14).
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
3. Access to an external area in single-chip mode
Table 23.7 Ready Flag Format
Bit 3
Fixed at 0
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Command error
Bit 0
0: Not ready
1: Ready
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1000
A3 to
A0
DIR
Input/output changeover
A31 to
A28
0000
Not Ready
0001
Ready
0001 0001
D3 to
D0
D7 to
D4
Ready Ready
Input
Output
Figure 23.12 Example of Read Operation (Byte Read)
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1110
A3 to
A0
DIR
A31 to D3 to
A28 D0
Input/output changeover
D31 to
D28
0000
Not Ready
0001
Ready
0001 0001
Ready Ready
Input
Output
Figure 23.13 Example of Write Operation (Longword Write)
Rev. 3.00 Oct. 06, 2008 Page 950 of 1080
REJ09B0230-0300