SH7147 Datasheet, PDF (251/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
• When DTC/AUD activation request is generated during read access to external space from CPU
Internal bus
Read access to external
space from CPU
DTC/AUD
External bus
DTC/AUD
activation request
Read access to external
space from CPU
DTC/AUD activation request is generated in this period.
• When DTC/AUD activation request is generated during write access to external space from CPU (1)
Internal bus
Write to external
space from CPU
DTC/AUD
External bus
DTC/AUD
activation request
Write access to external
space from CPU
DTC/AUD activation request is generated in this period.
• When DTC/AUD activation request is generated during write access to external space from CPU (2)
(When external space read request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external
space from CPU
Read access to external
space from CPU
DTC/AUD
External bus
DTC/AUD
activation request
Write access to external
space from CPU
Read access to external
space from CPU
DTC/AUD activation request is generated in this period.
• When DTC/AUD activation request is generated during write access to external space from CPU (3)
(When external space write request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external Write to external
space 1 from CPU space 2 from CPU
DTC/AUD
External bus
DTC/AUD
activation request
Write access to external
space 1 from CPU
Write access to external
space 2 from CPU
DTC/AUD activation request is generated in this period.
Figure 9.10 Bus Arbitration when DTC or AUD Activation Request Occur during External
Space Access from CPU
Rev. 3.00 Oct. 06, 2008 Page 227 of 1080
REJ09B0230-0300