SH7147 Datasheet, PDF (653/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
(3) Data Reception
Figure 14.15 shows an example of reception operation, and figure 14.16 shows a flowchart
example of data reception. When receiving data, the synchronous serial communication unit
operates as shown below.
After setting the RE bit in SSER to 1, the synchronous serial communication unit starts data
reception.
In master mode, the synchronous serial communication unit outputs a transfer clock and receives
data. In slave mode, when a transfer clock is input to the SSCK pin, the synchronous serial
communication unit receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
SSCK
SSO
RDRF
Bit 0
1 frame
Bit 7
Bit 0
1 frame
Bit 7
Bit 0
Bit 7
LSI operation
User operation Dummy-read SSRDR
RXI interrupt
generated
RXI interrupt
generated
Read data from SSRDR
RXI interrupt
generated
Read data from SSRDR
Figure 14.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
Rev. 3.00 Oct. 06, 2008 Page 629 of 1080
REJ09B0230-0300