SH7147 Datasheet, PDF (144/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
6.8.3
Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not DTC
Activation
1. For DTC, clear the corresponding DTCE bits to 0.
2. When an interrupt occurs, an interrupt request is sent to the CPU.
3. The CPU clears the interrupt source and performs the necessary processing in the interrupt
handling routine.
6.9 Usage Note
The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt
source that should have been cleared is not inadvertently accepted again, read the interrupt source
flag after it has been cleared, confirm that it has been cleared, and then execute an RTE
instruction.
Rev. 3.00 Oct. 06, 2008 Page 120 of 1080
REJ09B0230-0300