SH7147 Datasheet, PDF (754/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
17.5 Interrupt Sources
Table 17.2 lists the RCAN-ET interrupt sources. With the exception of the reset processing
interrupt (IRR0) by a power-on reset, these sources can be masked. Masking is implemented using
the mailbox interrupt mask register 0 (MBIMR0) and interrupt mask register (IMR). For details on
the interrupt vector of each interrupt source, see section 6, Interrupt Controller (INTC).
Table 17.2 RCAN-ET Interrupt Sources
Module
Interrupt Description
Interrupt
Flag
DTC
Activation
RCAN-ET_0 ERS_0 Error Passive Mode (TEC ≥ 128 or REC ≥ IRR5
128)
Not possible
Bus Off (TEC ≥ 256)/Bus Off recovery
IRR6
Error warning (TEC ≥ 96)
IRR3
Error warning (REC ≥ 96)
IRR4
OVR_0 Message error detection
IRR13*¹
Reset/halt/CAN sleep transition
IRR0
Overload frame transmission
IRR7
Unread message overwrite (overrun)
IRR9
Detection of CAN bus operation in CAN
sleep mode
IRR12
RM0_0*² Data frame reception
RM1_0*² Remote frame reception
IRR1*³
IRR2*³
Possible*⁴
SLE_0
Message transmission/transmission
disabled (slot empty)
IRR8
Not possible
Notes: 1. Available only in Test Mode.
2. RM0_0 is an interrupt generated by the remote request pending flag for mailbox 0
(RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1_0 is an
interrupt generated by the remote request pending flag for mailbox n (RFPR0[n]) or the
data frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 15).
3. IRR1 is a data frame received interrupt flag for mailboxes 0 to 15, and IRR2 is a remote
frame request interrupt flag for mailboxes 0 to 15.
4. The DTC can be activated only by the RM0_0 interrupt.
Rev. 3.00 Oct. 06, 2008 Page 730 of 1080
REJ09B0230-0300