SH7147 Datasheet, PDF (887/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Flash Memory
(1.2) SCO download request and interrupt request
Download of the on-chip programming/erasing program that is initiated by setting the SCO bit
in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover.
Operation when the SCO download request and interrupt request conflicts is described below.
1. Contention between SCO download request and interrupt request
Figure 20.21 shows the timing of contention between execution of the instruction that sets
the SCO bit in FCCS to 1 and interrupt acceptance.
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
n
Fetch
n+1
Decoding
(a)
n+2
Execution
n+3
Execution
(b)
n+4
Execution
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Figure 20.21 Timing of Contention between SCO Download Request and Interrupt Request
2. Generation of interrupt requests during downloading
Ensure that interrupts are not generated during downloading that is initiated by the SCO
bit.
(2) Interrupts during Programming/Erasing
Interrupts during execution of write or erase operations with a downloaded on-chip program and
acquisition of bus rights by bus masters other than the CPU are forbidden.
Rev. 3.00 Oct. 06, 2008 Page 863 of 1080
REJ09B0230-0300