SH7147 Datasheet, PDF (537/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
(2) Low-Level Detection
Figure 11.3 shows the low-level detection operation. Sixteen continuous low levels are sampled
with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this
interval, the low level is not accepted.
The timing when the special pins of the MTU2 and MTU2S enter the high-impedance state after
the sampling clock is input is the same in both falling-edge detection and in low-level detection.
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
High-impedance
state*
When low level is
Flag set
sampled at all points ¹
2
3
16 _{(POE received)}
When high level is
sampled at least once
1
2
13 Flag not set
Note: * Other special pins of MTU2 and MTU2S also enter the high-impedance state with the same timing.
Figure 11.3 Low-Level Detection Operation
11.4.2 Output-Level Compare Operation
Figure 11.4 shows an example of the output-level compare operation for the combination of
TIOC3B and TIOC3D. The operation is the same for the other pin combinations.
Pφ
PE9/
TIOC3B
PE11/
TIOC3D
Low level overlapping detected
High impedance state
Figure 11.4 Output-Level Compare Operation
Rev. 3.00 Oct. 06, 2008 Page 513 of 1080
REJ09B0230-0300