SH7147 Datasheet, PDF (889/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Flash Memory
(4) State in which interrupts are ignored
In the following modes or period, interrupt requests are ignored; they are not executed and the
interrupt sources are not retained.
• Boot mode
• Programmer mode
(5) Note on programming the product having a 384-Kbyte/256-Kbyte user MAT
If an attempt is made to program the product having a 384-Kbyte user MAT with more than 384
Kbytes, data programmed after the first 384 Kbytes are not guaranteed.
If an attempt is made to program the product having a 256-Kbyte user MAT with more than 256
Kbytes, data programmed after the first 256 Kbytes are not guaranteed.
(6) Compatibility with programming/erasing program of conventional F-ZTAT SH
microcomputer
A programming/erasing program for flash memory used in the conventional F-ZTAT SH
microcomputer which does not support download of the on-chip program by a SCO transfer
request cannot run in this LSI.
Be sure to download the on-chip program to execute programming/erasing of flash memory in this
LSI.
(7) Monitoring runaway by WDT
Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a
runaway by WDT during programming/erasing by the downloaded on-chip program.
Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for
WDT while taking the programming/erasing time into consideration as required.
(8) Stack address
The stack start address must be in internal RAM during write or erase operations.
(9) Illegal access areas when the RAM emulation function is used
When the RAM emulation function is used, accesses to the areas listed in table 20.13 are illegal.
Rev. 3.00 Oct. 06, 2008 Page 865 of 1080
REJ09B0230-0300