SH7147 Datasheet, PDF (517/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
11.3.1 Input Level Control/Status Register 1 (ICSR1)
ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE2 pin input modes,
controls the enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10
- POE2F POE1F POE0F -
-
Initial value: 0
0
0
0
0
0
R/W: R R/(W)*¹R/(W)*¹ R/(W)*¹ R
R
9
8
7
- PIE1 -
0
0
0
R R/W R
6
5
4
3
2
1
0
-
POE2M[1:0] POE1M[1:0] POE0M[1:0]
0
0
0
0
0
0
0
R R/W*² R/W*² R/W*² R/W*² R/W*² R/W*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Initial
Bit Bit Name value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
POE2F
0
R/(W)*¹ POE2 Flag
This flag indicates that a high impedance request has
been input to the POE2 pin.
[Clearing conditions]
• By writing 0 to POE2F after reading POE2F = 1
(when the falling edge is selected by bits 5 and 4 in
ICSR1)
• By writing 0 to POE2F after reading POE2F = 1 after
a high level input to POE2 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 5 and 4 in ICSR1)
[Setting condition]
• When the input set by ICSR1 bits 5 and 4 occurs at
the POE2 pin
Rev. 3.00 Oct. 06, 2008 Page 493 of 1080
REJ09B0230-0300