SH7147 Datasheet, PDF (704/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
Table 17.1 Roles of Mailboxes
Tx
Rx
MB15-1
OK
OK
MB0
⎯
OK
MB0 (reception MB)
Byte: 8-bit access, Word: 16-bit access, LW (LongWord): 32-bit access
Address
Data Bus
Access Size
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field Name
H'100 + N*32 IDE RTR 0
STDID[10:0]
H'102 + N*32
H'104 + N*32
IDE_
LAFM
0
0
H'106 + N*32
EXTID[15:0]
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
H'108 + N*32
MSG_DATA_0 (first Rx/Tx Byte)
H'10A + N*32
MSG_DATA_2
H'10C + N*32
MSG_DATA_4
H'10E + N*32
MSG_DATA_6
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
EXTID[17:16] Word/LW
EXTID_
LAFM[17:16]
Word
Word/LW
Word
Byte/Word/LW
Byte/Word
Byte/Word/LW
Byte/Word
Control 0
LAFM
Data
H'110 + N*32 0 0 NMC 0 0
MBC[2:0]
000 0
DLC[3:0]
Byte/Word
Control 1
MB15-1 (MB for transmission/reception)
MBC[1] is fixed to "1"
Address
Data Bus
Access Size
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field Name
H'100 + N*32 IDE RTR 0
STDID[10:0]
H'102 + N*32
H'104 + N*32
IDE_
LAFM
0
0
H'106 + N*32
EXTID[15:0]
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
H'108 + N*32
MSG_DATA_0 (first Rx/Tx Byte)
H'10A + N*32
MSG_DATA_2
H'10C + N*32
MSG_DATA_4
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
EXTID[17:16] Word/LW
EXTID_
LAFM[17:16]
Word
Word/LW
Word
Byte/Word/LW
Byte/Word
Byte/Word/LW
Control 0
LAFM
Data
H'10E + N*32
H'110 + N*32 0
MSG_DATA_6
0 NMC ATX DART
MBC[2:0]
MSG_DATA_7
000 0
DLC[3:0]
Byte/Word
Byte/Word
Control 1
Figure 17.3 Mailbox-N Structure
Notes: 1. All bits shadowed in grey are reserved and must be written LOW. The value returned
by a read may not always be ‘0’ and should not be relied upon.
2. ATX and DART are not supported by Mailbox-0, and the MBC setting of Mailbox-0 is
limited.
3. ID Reorder (MCR15) can change the order of STDID, RTR, IDE and EXTID of both
message control and LAFM.
Rev. 3.00 Oct. 06, 2008 Page 680 of 1080
REJ09B0230-0300