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SH7147 Datasheet, PDF (700/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 17 Controller Area Network (RCAN-ET)
Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole
RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
⢠Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and RCAN-ETâs
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so
that the RCAN-ET can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
⢠Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 16
Mailboxes, and each mailbox has the following information.
<RAM>
⯠CAN message control (identifier, rtr, ide, etc)
⯠CAN message data (for CAN Data frames)
⯠Local Acceptance Filter Mask for reception
<Registers>
⯠CAN message control (dlc)
⯠3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
Transmission for Remote Request bit, New Message Control bit
⢠Mailbox Control
The Mailbox Control handles the following functions:
⯠For received messages, compare the IDs and generate appropriate RAM addresses/data to
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
⯠To transmit messages, RCAN-ET will run the internal arbitration to pick the correct
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly.
⯠Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
⯠Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
MBIMR.
Rev. 3.00 Oct. 06, 2008 Page 676 of 1080
REJ09B0230-0300
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