SH7147 Datasheet, PDF (959/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
23.3.7 AUD Extended Control Register (AUECSR)
AUECSR is a 32-bit readable/writable register. AUECSR is initialized by a power-on reset,
manual reset, AUDRST, AUD software reset, and hardware standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
-
-
-
-
-
- WAOB -
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R
7
6
5
- WBOB -
0
0
0
R R/W R
4
3
2
1
0
- TREX TRSB TRGN -
0
0
0
0
1
R R/W R/W R/W R
Bit
Bit Name
31 to 10 ⎯
9
WAOB
8, 7
⎯
6
WBOB
Initial
Value
All 0
0
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Window A Trace Bus Select
Specifies which internal bus data trace should be
executed in window A.
0: Specifies the L bus
1: Specifies the I bus
Note: Be sure to change this bit while the EN bit in
AUCSR is 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Window B Trace Bus Select
Specifies which internal bus data trace should be
executed in window B.
0: Specifies the L bus
1: Specifies the I bus
Note: Be sure to change this bit while the EN bit in
AUCSR is 0
Rev. 3.00 Oct. 06, 2008 Page 935 of 1080
REJ09B0230-0300