SH7147 Datasheet, PDF (164/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
3
SEQ
0
R/W Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential conditions.
0: Channels A and B are compared under independent
conditions
1: Channels A and B are compared under sequential
conditions (channel A, then channel B)
2, 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ETBE
0
R/W Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break is
issued when the number of break conditions matches
with the number of execution times that is specified by
BETR.
0: The execution-times break condition is disabled on
channel B
1: The execution-times break condition is enabled on
channel B
Note: The operand size must be specified if the data bus value is included in the break condition
and the interrupt cycle is specified in the break condition with the RWA and/or RWB bits.
Rev. 3.00 Oct. 06, 2008 Page 140 of 1080
REJ09B0230-0300