SH7147 Datasheet, PDF (239/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5 Operation
9.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
The data bus width is 8 bits. Data alignment is performed in accordance with the data bus width of
the respective device. This also means that when longword data is read from a byte-width device,
the read operation must be done four times. In this LSI, data alignment and conversion of data
length are performed automatically between the respective interfaces.
Table 9.7 shows the relationship between device data width and access unit.
Table 9.7 8-Bit External Device Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word
access
at 0
1st time at 0
2nd time at 1
Word
access
at 2
1st time at 2
2nd time at 3
Longword
access
at 0
1st time at 0
2nd time at 1
3rd time at 2
4th time at 3
Data Bus
D7 to D0
Data 7 to Data 0
Data 7 to Data 0
Data 7 to Data 0
Data 7 to Data 0
Data 15 to Data 8
Data 7 to Data 0
Data 15 to Data 8
Data 7 to Data 0
Data 31 to Data 24
Data 23 to Data 16
Data 15 to Data 8
Data 7 to Data 0
Strobe Signals
WRL
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Rev. 3.00 Oct. 06, 2008 Page 215 of 1080
REJ09B0230-0300