SH7147 Datasheet, PDF (868/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Flash Memory
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
set to the FUBRA parameter for initialization.
1. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
R4). For the settable range of the FPEFEQ parameter, see section 25.3.1, Clock Timing.
When the frequency is set out of this range, an error is returned to the FPFR parameter of
the initialization program and initialization is not performed. For details on the frequency
setting, see the description of Flash programming/erasing frequency parameter (FPEFEQ:
general register R4 of CPU) in section 20.4.3 (2), Programming/Erasing Initialization.
2. The start address in the user branch destination is set to the FUBRA parameter (general
register R5).
When the user branch processing is not required, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in flash memory other
than the one that is to be programmed. The area of the on-chip program that is downloaded
cannot be set.
The program processing must be returned from the user branch processing by the RTS
instruction.
See the description of Flash user branch address setting parameter (FUBRA: general
register R5 of CPU) in section 20.4.3 (2), Programming/Erasing Initialization.
(2.7) Initialization
When a programming program is downloaded, the initialization program is also downloaded to
on-chip RAM. There is an entry point of the initialization program in the area from (download
start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed
by using the following steps.
MOV.L #DLTOP+32,R1
JSR @R1
NOP
; Set entry address to R1
; Call initialization routine
1. The general registers other than R0 are saved in the initialization program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the initialization program, a stack area of maximum 128
bytes must be reserved in RAM.
4. Interrupts can be accepted during the execution of the initialization program. However, the
program storage area and stack area in on-chip RAM and register values must not be
destroyed.
(2.8) The return value of the initialization program, FPFR (general register R0) is checked.
(2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming.
(2.10) The parameter which is required for programming is set.
Rev. 3.00 Oct. 06, 2008 Page 844 of 1080
REJ09B0230-0300