SH7147 Datasheet, PDF (90/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 24, List of Registers.
Table 4.5 Register Configuration
Register Name
Frequency control register
Oscillation stop detection
control register
Abbrevia-
tion
FRQCR
OSCCR
R/W
R/W
R/W
Initial Value Address
H'36DB
H'FFFFE800
H'00
H'FFFFE814
Access Size
16
8
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the
internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock
(MPφ). FRQCR can be accessed only in words.
FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT
overflow).
Bit: 15
-
Initial value: 0
R/W: R
14 13 12
IFC[2:0]
0
1
1
R/W R/W R/W
11 10 9
BFC[2:0]
0
1
1
R/W R/W R/W
8
7
6
PFC[2:0]
0
1
1
R/W R/W R/W
5
4
3
MIFC[2:0]
0
1
1
R/W R/W R/W
2
1
0
MPFC[2:0]
0
1
1
R/W R/W R/W
Rev. 3.00 Oct. 06, 2008 Page 66 of 1080
REJ09B0230-0300