SH7147 Datasheet, PDF (660/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 A/D Converter (ADC)
Figure 15.1 shows a block diagram of the A/D converter.
A/D_0
Internal data bus
Bus interface
AVcc
AVss
AVrefh
AVrefl
12-bit D/A
AVcc
AVss
AVrefh
AVrefl
AN0
GrA AN1
AN2
AN3
AN4
AN5
AN6
AN7
Sample-and-
hold circuit
Sample-and-
hold circuit
Sample-and-
hold circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Sample-and-
hold circuit
+
Comparator
−
Offset cancel circuit
A/D_1
Internal data bus
Bus interface
AVcc
AVss
AVrefh
AVrefl
12-bit D/A
A/D 0 conversion
control circuit
A/D conversion
end interrupt
signal (ADI_3)
A/D trigger signal
from MTU2
(TRGAN,
TRG0N,
TRG4AN,
TRG4BN)
A/D trigger signal
from MTU2S
(TRGAN,
TRG4AN,
TRG4BN)
AN8
GrB AN9
AN10
AN11
AN12
AN13
AN14
AN15
Sample-and-
hold circuit
Sample-and-
hold circuit
Sample-and-
hold circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Impedance-
conversion circuit
Sample-and-
hold circuit
+
Comparator
−
Offset cancel circuit
A/D 1 conversion
control circuit
External trigger signal
(ADTRG)
A/D conversion
end interrupt
signal (ADI_4)
[Legend]
ADDR: A/D data register
ADCR: A/D control register
ADANSR: A/D analog input channel select register
ADSR: A/D status register
ADSTRGR: A/D start trigger select register
GrA:
GrB:
Group A
Group B
Figure 15.1 Block Diagram of A/D Converter
Rev. 3.00 Oct. 06, 2008 Page 636 of 1080
REJ09B0230-0300