SH7147 Datasheet, PDF (544/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Watchdog Timer (WDT)
12.3 Register Descriptions
The WDT has the following two registers. Refer to section 24, List of Registers, for the details of
the addresses of these registers and the state of registers in each operating mode.
Table 12.2 Register Configuration
Register Name
Abbrevia-
tion
R/W Initial Value Address
Access Size
Watchdog timer counter
WTCNT R/W H'00
H'FFFFE810 8, 16
Watchdog timer control/status WTCSR
register
R/W H'00
H'FFFFE812 8, 16
12.3.1 Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time
mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The
WTCNT counter is initialized to H'00 only by a power-on reset using the RES pin. Use a word
access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read
WTCNT.
Note: WTCNT differs from other registers in that it is more difficult to write to. See section
12.3.3, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 3.00 Oct. 06, 2008 Page 520 of 1080
REJ09B0230-0300