SH7147 Datasheet, PDF (250/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
In addition, because the write buffer operates as described in section 9.5.7 (2), Access in View of
LSI Internal Bus Master, arbitration between the CPU and AUD/DTC is different depending on
whether the external space access by the CPU is a write or read access. Figure 9.10 shows the bus
arbitration when a AUD or DTC activation request is generated while an external space is
accessed by CPU.
Rev. 3.00 Oct. 06, 2008 Page 226 of 1080
REJ09B0230-0300