SH7147 Datasheet, PDF (247/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.8 Minimum Number of Idle Cycles between CPU Access Cycles in Normal Space
Interface
BSC Register Setting
When Access Size is Less than
Bus Width
When Access Size Exceeds Bus Width
Contin- Contin-
CSnWCR. CSnBCR Read to Write to Read to Write to uous uous Read to Write to Read to Write to
WM Setting Idle Setting Read Write Write Read Read*¹ Write*¹ Read*² Write*² Write*² Read*²
1
0
1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0 0/0/0/0 0/0/0/0 1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0
0
0
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
1
1
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
0
1
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
1
2
2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2
0
2
2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2
1
4
4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4
0
4
4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4
Notes:
The minimum numbers of idle cycles are described sequentially for Iφ:Bφ = 4:1, 3:1, 2:1,
and 1:1.
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
32-bit access cycle when the bus width is 16 bits
2. Other than the above cases
Rev. 3.00 Oct. 06, 2008 Page 223 of 1080
REJ09B0230-0300