SH7147 Datasheet, PDF (888/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Flash Memory
20.8.3 Other Notes
(1) Download time of on-chip program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock
frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum.
(2) User branch processing intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 20.11 lists the maximum intervals for initiating the user
branch processing when the CPU clock frequency is 64 to 80 MHz.
Table 20.11 Initiation Intervals of User Branch Processing
Processing Name
Programming
Erasing
Maximum Interval
Approximately 2 ms
Approximately 15 ms
However, when operation is done with CPU clock of 64 to 80 MHz, the maximum values of the
time until first user branch processing are as shown in table 20.12.
Table 20.12 Initial User Branch Processing Time
Processing Name
Programming
Erasing
Max.
Approximately 2 ms
Approximately 15 ms
(3) Write to flash-memory related registers by DTC
While an instruction in on-chip RAM is being executed, the DTC can write to the SCO bit in
FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure
that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and destroy RAM or a MAT switchover may occur and the CPU get out of control.
Rev. 3.00 Oct. 06, 2008 Page 864 of 1080
REJ09B0230-0300