SH7147 Datasheet, PDF (235/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
18
⎯
0
R
17, 16 IWRRS[1:0] 11
R/W
15 to 11 ⎯
All 0 R
10, 9 BSZ[1:0] 11
R/W
8 to 0 ⎯
All 0 R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Read
Cycles in the Same Space
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-read cycles in the
same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
These bits are always read as 0. The write value should
always be 0.
Data Bus Size Specification
Specify the data bus sizes of spaces. When the on-chip
ROM is enabled, write B'01 to these bits to specify the
8-bit data bus width before accessing the CSn space.
Note: When the on-chip ROM is disabled, the data bus
width in area 0 is specified through external
input pins. The BSZ1 and BSZ0 bit setting in
CS0BCR is ignored.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 211 of 1080
REJ09B0230-0300