SH7147 Datasheet, PDF (639/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.4.5 Synchronous Serial Communication Mode
In synchronous serial communication mode, data communications are performed via four lines:
clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line
(SCS).
In addition, the synchronous serial communication unit supports bidirectional mode in which a
single pin functions as data input and data output lines.
(1) Initial Settings in Synchronous Serial Communication Mode
Figure 14.4 shows an example of the initial settings in synchronous serial communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note:
Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Rev. 3.00 Oct. 06, 2008 Page 615 of 1080
REJ09B0230-0300