SH7147 Datasheet, PDF (960/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
Initial
Bit
Bit Name Value R/W Description
5, 4
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
TREX
0
R/W Exception Branch Trace Select
Specifies whether to trace exception branch
(exception, interrupt, or TRE instruction) during branch
trace
0: Traces exception branch
1: Does not trace exception branch
2
TRSB
0
R/W Subroutine Branch Trace Select
Specifies whether to trace subroutine branch (BSR,
BSRF, JSR, or RTS instruction) during branch trace
0: Traces subroutine branch
1: Does not trace subroutine branch
1
TRGN
0
R/W General Branch Trace Select
Specifies whether to trace general branch (BF, BT,
BF/S, BT/S, BRA, BRAF, or JMP instruction) during
branch trace
0: Traces general branch
1: Does not trace general branch
0
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 3.00 Oct. 06, 2008 Page 936 of 1080
REJ09B0230-0300