SH7147 Datasheet, PDF (213/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in
transfer information plus 1).
Number of execution cycles = I • S_I + Σ (J • S_J + K • S_K + L • S_L + M • S_M) + N • S_N
8.5.9 DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, transfer information read, a single data transfer, or
transfer information write-back. The DTC does not release the bus mastership during transfer
information read, a single data transfer, or write-back of transfer information.
The bus release timing can be specified through the bus function extending register (BSCEHR).
For details see section 9.4.4, Bus Function Extending Register (BSCEHR). The difference in bus
release timing according to the register setting is summarized in table 8.11. The value of BSCEHR
must not be modified while the DTC is active.
Figure 8.13 is a timing chart showing an example of bus release timing.
Table 8.11 DTC Bus Release Timing
Bus Function
Extending Register
(BSCEHR) Setting
Bus Release Timing
(O: Bus must be released;
Δ: Bus is released depending on the CPU execution status,
x: Bus is not released)
Bit 15
(DTLOCK)
After
vector
read
NOP
issuance*
After
transfer After a
information single data
read
transfer
After write-back of
transfer information
Normal Continuous
transfer transfer
Setting 1 1
O
O
Δ
Δ
O
O
Setting 2 0
x
O
x
x
O
O
Note: * Bus is only released for the external access request from the CPU after a vector read.
Rev. 3.00 Oct. 06, 2008 Page 189 of 1080
REJ09B0230-0300