SH7147 Datasheet, PDF (36/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Classification
Symbol
I/O
Interrupts
NMI
I
IRQ3 to IRQ0 I
IRQOUT
O
Address bus
Data bus
Bus control
A19 to A0 O
D7 to D0 I/O
CS1, CS0 O
RD
O
WRL
O
WAIT
I
Multi function timer- TCLKA,
I
pulse unit 2 (MTU2) TCLKB,
TCLKC,
TCLKD
TIOC0A,
I/O
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
I/O
TIOC1B
Name
Function
Non-maskable
interrupt
Non-maskable interrupt request pin
Fix to high or low level when not in
use.
Interrupt requests Maskable interrupt request pin
3 to 0
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Interrupt request
output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
Address bus
Outputs addresses
Data bus
Bidirectional bus
Chip select 1 and Chip-select signal for external
0
memory or devices
Read
Indicates reading of data from
external devices.
Write to lower
byte
Indicates a write access to bits 7 to 0
of the external data.
Wait
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space
MTU2 timer clock External clock input pins for the timer
input
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins
The TGRA_1 to TGRB_1 input
capture input/output compare
output/PWM output pins
Rev. 3.00 Oct. 06, 2008 Page 12 of 1080
REJ09B0230-0300