SH7147 Datasheet, PDF (391/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) and Multi-Function Timer Pulse Unit 2S (MTU2S)
TGRC_3 TCBR
TDDR TGRA_3 TCDR
Comparator
TCNT_3 TCNTS TCNT_4
Comparator
Match
signal
Match
signal
PWM cycle
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
External cutoff
input
POE0
POE1
POE2
TGRD_3
TGRC_4
TGRD_4
External cut off
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by TRWER)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Figure 10.38 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
Rev. 3.00 Oct. 06, 2008 Page 367 of 1080
REJ09B0230-0300