SH7147 Datasheet, PDF (238/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
5 to 2
1, 0
Initial
Bit Name Value R/W Description
⎯
All 0
R
Reserved
HW[1:0] 00
These bits are always read as 0. The write value should
always be 0.
R/W Delay Cycles from RD and WRL Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRL
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
9.4.4 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTLOCK -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
15
DTLOCK 0
R/W
14 to 0 ⎯
All 0 R
Description
DTC Lock Enable
Specifies the timing of bus release by the DTC.
0: The DTC releases the bus on issuance of NOP after
vector read or write-back of transfer information.
1: The DTC releases the bus after vector read, on
issuance of NOP after vector read, after transfer
information read, after a single data transfer, or after
write-back of transfer information.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 214 of 1080
REJ09B0230-0300