SH7147 Datasheet, PDF (240/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.2 Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of
the fact that mainly SRAM without a byte selection will be directly connected. Figure 9.2 shows
the basic timings of normal space access. A no-wait normal access is completed in two cycles.
T1
T2
CK
A19 to A0
CSn
Read
RD
D7 to D0
Write
WRL
D7 to D0
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 8 bits are always
read. When writing, only the WRL signal for the byte to be written is asserted.
It is necessary to control of outputing the data that has been read using RD when a buffer is
established in the data bus.
Rev. 3.00 Oct. 06, 2008 Page 216 of 1080
REJ09B0230-0300