SH7147 Datasheet, PDF (975/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1010
A3 to
A0
DIR
Input/output changeover
A31 to
A28
0000
Not Ready
0101
0101 0101
Ready
(Bus error)
Ready
(Bus error)
Input
Output
Figure 23.14 Example of Error Occurrence (Longword Read)
23.4.3 Usage Notes (RAM Monitor Mode)
(1) Guidelines for Initialization of the RAM Monitor Mode
The buffers in the AUD and the processing status are initialized under the following conditions.
• Power-on reset
• Manual reset
• Hardware standby
• When the AUDRST pin is driven to low
• Software reset (when the AUDSRST bit in STBCR6 is cleared to 0)
(2) Guidelines for AUDCK
• AUDCK is for inputting the external clock. Input the clock to be used for debugging.
• Set the frequency of AUDCK to satisfy the following conditions: lower than or equal to both
10 MHz and 1/4 of Pφ.
(3) Other Limitations
• Do not assert AUDSYNC until the command is input and the necessary data is prepared.
• Do not shift the AUD to the software standby mode while the SRAM monitor function is
working.
• When the pin function of the AUD is selected through the pin function controller (PFC), do not
shift the AUD to the module standby mode.
Rev. 3.00 Oct. 06, 2008 Page 951 of 1080
REJ09B0230-0300