SH7147 Datasheet, PDF (965/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
In either of the three cases, the same signal is output to CMD1, CMD2, and PID, such that BPC
(B'0010) is output to CMD1 and (ssa)/(sda) to CMD2.
When outputting the branch destination only, the branch destination address of the previous
branch is subject to comparison, not the branch source address of the previous branch.
In a user program, branch data is not output while branch events (such as execution of a branch
instruction and interrupts) are not generated. When branch events are generated, AUDATA[3:0]
outputs the trace data in the order of command, branch destination address, branch source address,
and PID. Address sizes output for both branch destination and branch source (4/8/16/32 bits) are
determined by comparing the upper bits of both addresses based on the value of PFBA (branch
destination output previous time).
The algorithm is shown in figure 23.5.
[Legend]
PFBA: Branch destination address output previous time
CDA: Branch destination address output this time
CSA: Branch source address output this time
PID: Compensation value to generate correct branch source address
TSA: Correct branch source address
********************************************************************************************
/* PFBA_enable = 0: initial value */
if(PFBA_enable == 0) {output32bit(CDA[31:0]);}
else if(PFBA[31:4] == CDA[31:4]) {output4bit(CDA[3:0]);}
else if(PFBA[31:8] == CDA[31:8]) {output8bit(CDA[7:0]);}
else if(PFBA[31:16] == CDA[31:16]) {output16bit(CDA[15:0]);}
else {output32bit(CDA[31:0]);}
if(PFBA_enable == 0) {output32bit(CSA[31:0]);}
else if(PFBA[31:4] == CSA[31:4]) {output4bit(CSA[3:0]);}
else if(PFBA[31:8] == CSA[31:8]) {output8bit(CSA[7:0]);}
else if(PFBA[31:16] == CSA[31:16]) {output16bit(CSA[15:0]);}
else {output32bit(CSA[31:0]);}
PFBA_enable = 1;
PFBA = CDA; /* update PFBA */
********************************************************************************************
Calculate actual branch source address using the following equation.
TSA = CSA.(2*PID)
Figure 23.5 Branch Trace Algorithm
This algorithm can greatly reduce the amount of trace data to be output. Branch trace data is stored
in FIFO as long as FIFO has room to store it. The CPU operation when FIFO becomes full
depends upon the setting of the TM bit in AUCSR.
Rev. 3.00 Oct. 06, 2008 Page 941 of 1080
REJ09B0230-0300