SH7147 Datasheet, PDF (93/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
4.4.2 Oscillation Stop Detection Control Register (OSCCR)
OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects
flag status output to an external pin. OSCCR can be accessed only in bytes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
OSC
STOP
-
OSC
ERS
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W
Bit
7 to 3
Initial
Bit Name Value R/W
⎯
All 0
R
2
OSCSTOP 0
R
1
⎯
0
R
0
OSCERS 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Oscillation Stop Detection Flag
[Setting conditions]
• When a stop in the clock input is detected during
normal operation
• When software standby mode is entered
[Clearing conditions]
• By a power-on reset input through the RES pin
• When software standby mode is canceled
Reserved
This bit is always read as 0. The write value should
always be 0.
Oscillation Stop Detection Flag Output Select
Selects whether to output the oscillation stop
detection flag signal through the WDTOVF pin.
0: Outputs only the WDT overflow signal through the
WDTOVF pin
1: Outputs the WDT overflow signal and the
oscillation stop detection flag signal through the
WDTOVF pin
Rev. 3.00 Oct. 06, 2008 Page 69 of 1080
REJ09B0230-0300