SH7147 Datasheet, PDF (35/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Classification
Operating mode
control
System control
Symbol
I/O Name
Function
MD1, MD0 I
Mode set
Sets the operating mode. Do not
change values on these pins during
operation.
FWE
I
Flash memory Pin for flash memory
write enable
Flash memory can be protected
against programming or erasure
through this pin.
RES
MRES
HSTBY
I
Power-on reset When low, this LSI enters the power-
on reset state.
I
Manual reset When low, this LSI enters the
manual reset state.
I
Hardware
standby
When low, this LSI enters hardware
standby mode. When no signal is
input through this pin, it is pulled up
inside this LSI.
High level must be input to this pin
while the chip is being powered up.
WDTOVF O Watchdog timer Output signal for the watchdog timer
overflow
overflow
BREQ
BACK
Since this pin stays in a Hi-Z state
for a while after deep standby mode
is exited, this pin must be pulled up.
I
Bus-mastership Low when an external device
request
requests the release of the bus
mastership.
O Bus-mastership Indicates that the bus mastership
request
acknowledge
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Rev. 3.00 Oct. 06, 2008 Page 11 of 1080
REJ09B0230-0300