SH7147 Datasheet, PDF (733/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
The RCAN-ET will clear a transmit pending flag after successful transmission of its
corresponding message or when a transmission abort is requested successfully from the TXCR.
The TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the
arbitration process or due to errors on the CAN bus, and RCAN-ET automatically tries to transmit
it again unless its DART bit (Disable Automatic Re-Transmission) is set in the Message-Control
of the corresponding Mailbox. In such case (DART set), the transmission is cleared and notified
through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort
Acknowledgement Register (ABACK).
If the status of the TXPR changes, the RCAN-ET shall ensure that in the identifier priority scheme
(MCR2=0), the highest priority message is always presented for transmission in an intelligent way
even under circumstances such as bus arbitration losses or errors on the CAN bus. Please refer to
section 17.4, Application Note.
When the RCAN-ET changes the state of any TXPR bit position to a '0', an empty slot interrupt
(IRR8) may be generated. This indicates that either a successful or an aborted mailbox
transmission has just been made. If a message transmission is successful it is signalled in the
TXACK register, and if a message transmission abortion is successful it is signalled in the
ABACK register. By checking these registers, the contents of the Message of the corresponding
Mailbox may be modified to prepare for the next transmission.
• TXPR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXPR1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Any write operation is ignored.
Read value is always H'0000. Long word access is mandatory when reading or writing
TXPR1/TXPR0. Writing any value to TXPR1 is allowed, however, write operation to TXPR1 has
no effect.
• TXPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXPR0[15:1]
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* -
Note : * it is possible only to write a ‘1’ for a Mailbox configured as transmitter.
Rev. 3.00 Oct. 06, 2008 Page 709 of 1080
REJ09B0230-0300