SH7147 Datasheet, PDF (515/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
Table 11.2 shows output-level comparisons with pin combinations.
Table 11.2 Pin Combinations
Pin Combination
I/O
Description
PE9/TIOC3B and PE11/TIOC3D
PE12/TIOC4A and PE14/TIOC4C
PE13/TIOC4B and PE15/TIOC4D
Output
The special pins for the MTU2 are placed in the
high-impedance state when the pins
simultaneously output an active level (low level
when the output level select P (OLSP) bit of the
timer output control register (TOCR) in the MTU2 is
0 or high level when the bit is 1) for one or more
cycles of the peripheral clock (Pφ).
This active level comparison is done when the
MTU2 output function or general output function is
selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and high-
impedance control can be selected by POE
registers.
PE16/TIOC3BS and PE17/TIOC3DS Output
PE18/TIOC4AS and PE20/TIOC4CS
PE19/TIOC4BS and PE21/TIOC4DS
The special pins for the MTU2S are placed in the
high-impedance state when the pins
simultaneously output an active level (low level
when the output level select P (OLSP) bit of the
timer output control register (TOCR) in the MTU2S
is 0 or high level when the bit is 1) for one or more
cycles of the peripheral clock (Pφ).
This active level comparison is done when the
MTU2S output function or general output function
is selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and high-
impedance control can be selected by POE
registers.
Rev. 3.00 Oct. 06, 2008 Page 491 of 1080
REJ09B0230-0300