SH7147 Datasheet, PDF (241/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Figures 9.3 and 9.4 show the basic timings of continuous accesses to normal space. If the WM bit
in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.3). If
the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.4).
T1
T2
Tnop
T1
T2
CK
A19 to A0
CSn
Read
RD
D7 to D0
Write
WRL
D7 to D0
WAIT
Figure 9.3 Continuous Access for Normal Space 1
Bus Width = 8 Bits, Longword Access, WM Bit in CSnWCR = 0
(Access Wait = 0, Cycle Wait = 0)
Rev. 3.00 Oct. 06, 2008 Page 217 of 1080
REJ09B0230-0300