SH7147 Datasheet, PDF (1093/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Main Revisions for This Edition
Main Revisions for This Edition
Item
7.3.11 Break Control Register
(BRCR)
10.1 Features
Table 10.2 MTU2S Functions
Page Revision (See Manual for Details)
139
Description amended
Initial
Bit
Bit Name Value R/W
7
DBEA
0
R/W
5
DBEB
0
R/W
Description
Data Break Enable A
Selects whether or not the data bus value is included
in the channel A break condition.
0: The data bus value is not included in the channel A
break condition
1: The data bus value is included in the channel A
break condition
Data Break Enable B
Selects whether or not the data bus value is included
in the channel B break condition.
0: The data bus value is not included in the channel B
break condition
1: The data bus value is included in the channel B
break condition
140 Note added
Note: The operand size must be specified if the data bus
value is included in the break condition and the
interrupt cycle is specified in the break condition with
the RWA and/or RWB bits.
241 Table amended
Item
PWM mode 1
Channel 3
—
Channel 4
Channel 5
—
15.3.2 A/D Status Registers_0 642
and _1 (ADSR_0 and ADSR_1)
Note added
Bit Bit Name
7 to 1
Initial
Value
All 0
0
ADF
0
R/W
R
R/(W)*
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
A/D End Flag
A status flag that indicates the completion of A/D
conversion.
[Setting condition]
• When A/D conversion on all specified channels is
completed in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt and
ADDR is read
Note: * Writing 0 to this bit after reading it as 1 clears the
flag and is the only allowed way. Do not overwrite
this bit with 0 when the value of this bit is 0.
Rev. 3.00 Oct. 06, 2008 Page 1069 of 1080
REJ09B0230-0300