SH7147 Datasheet, PDF (809/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 I/O Ports
19.2.2 Port B Data Register L (PBDRL)
PBDRL is a 16-bit readable/writable register that stores port B data. Bits PB7DR to PB0DR
correspond to pins PB7 to PB0 (multiplexed functions omitted here).
When a pin function is general output, if a value is written to PBDRL, that value is output directly
from the pin, and if PBDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PBDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PBDRL, although that value is written into PBDRL, it
does not affect the pin state. Table 19.4 summarizes port B data register read/write operations.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
DR DR DR DR DR DR DR DR
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 8 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
PB7DR 0
R/W See table 19.4
6
PB6DR 0
R/W
5
PB5DR 0
R/W
4
PB4DR 0
R/W
3
PB3DR 0
R/W
2
PB2DR 0
R/W
1
PB1DR 0
R/W
0
PB0DR 0
R/W
Rev. 3.00 Oct. 06, 2008 Page 785 of 1080
REJ09B0230-0300