SH7147 Datasheet, PDF (248/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.9 Minimum Number of Idle Cycles between Access Cycles during DTC Transfer
for the Normal Space Interface
BSC Register Setting
When Access Size is
Less than Bus Width
When Access Size Exceeds Bus Width
CSnWCR. CSnBCR Read to
WM Setting Idle Setting Write
Write to
Read
Continuous Read to
Read*¹
Write*²
Continuous Write to
Write*¹
Read*²
1
0
2
0
0
2
0
0
0
0
2
1
1
2
1
1
1
1
2
1
1
2
1
1
0
1
2
1
1
2
1
1
1
2
2
2
2
2
2
2
0
2
2
2
2
2
2
2
1
4
4
4
4
4
4
4
0
4
4
4
4
4
4
4
Notes:
DTC is operated by Bφ. The minimum number of idle cycles is not affected by changing
a clock ratio.
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
32-bit access cycle when the bus width is 16 bits
2. Other than the above cases.
9.5.6 Bus Arbitration
This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus
request from an external device. This LSI has three bus masters: CPU, AUD, and DTC. The bus
mastership is given to these bus masters in accordance with the following priority.
Request for bus mastership by external device (BREQ) > CPU > AUD > DTC
However, when DTC or AUD is requesting the bus mastership, the CPU does not obtain the bus
mastership continuously.
The external space access request from the CPU is noted as follow.
When an activation request is generated in the order of DTC and AUD while an external space is
being accessed by the CPU, DTC transfer is executed first. Figure 9.9 shows the bus arbitration
when the AUD and DTC compete while an external space is accessed by the CPU.
Rev. 3.00 Oct. 06, 2008 Page 224 of 1080
REJ09B0230-0300