SH7147 Datasheet, PDF (629/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
Initial
Bit
Bit Name Value R/W
0
CE
0
R/W
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (synchronous serial communication mode) and
MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0
(synchronous serial communication mode) and MSS =
0 (slave mode), an incomplete error occurs because it
is determined that a master device has terminated the
transfer. Data reception does not continue while the CE
bit is set to 1. Serial transmission also does not
continue. Reset the synchronous serial communication
unit internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting conditions]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
Rev. 3.00 Oct. 06, 2008 Page 605 of 1080
REJ09B0230-0300