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SH7147 Datasheet, PDF (212/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family
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Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
Object to be Accessed
On-Chip
RAM*1/ROM*2
On-Chip I/O
Registers
External Device*4
Bus width
32 bits
16 bits
8 bits
Access cycles
1Bφ to 3Bφ*1*2
2Pφ
2Bφ
Execu- Vector read SI
1Bφ to 3Bφ*1*2
⎯
tion
status
Transfer information read SJ
1Bφ to 3Bφ*1
⎯
Transfer information write Sk 1Bφ to 3Bφ*1
⎯
9Bφ
9Bφ
2Bφ*5
Byte data read SL
1Bφ to 3Bφ*1
1Bφ + 2Pφ*3
3Bφ
Word data read SL
1Bφ to 3Bφ*1
1Bφ + 2Pφ*3
5Bφ
Longword data read SL
1Bφ to 3Bφ*1
1Bφ + 4Pφ*3
9Bφ
Byte data write SM
1Bφ to 3Bφ*1
1Bφ + 2Pφ*3
2Bφ*5
Word data write SM
1Bφ to 3Bφ*1
1Bφ + 2Pφ*3
2Bφ*5
Longword data write SM
1Bφ to 3Bφ*1
1Bφ + 4Pφ*3
2Bφ*5
Internal operation SN
1
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of Iφ:Bφ.
Iφ:Bφ = 1:1
Iφ:Bφ = 1:1/2
Iφ:Bφ = 1:1/3
Iφ:Bφ = 1:1/4 or less
Read
3Bφ
2Bφ
2Bφ
1Bφ
Write
3Bφ
1Bφ
1Bφ
1Bφ
2. Values for on-chip ROM. Number of cycles varies depending on the ratio of Iφ:Bφ.and
are the same as on-chip RAM. Only vector read is possible.
3. The values in the table are those for the fastest case. Depending on the state of the
internal bus, replace 1Bφ by 1Pφ in a slow case.
4. Values are different depending on the BSC register setting. The values in the table are
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
5. Values are different depending on the bus state.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.7 (2), Access in View of LSI Internal Bus
Master.
Rev. 3.00 Oct. 06, 2008 Page 188 of 1080
REJ09B0230-0300
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