SH7147 Datasheet, PDF (950/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
Set the frequency of AUDCK clock to satisfy the following conditions: lower than or equal to both
10 MHz and Pφ × 1/4.
Before utilizing the AUD, clear the AUD software reset bit (AUDSRST) in the standby control
register 6 (STBCR6) to 0. For details on the AUDSRST bit, see section 22.3.6, Standby Control
Register 6 (STBCR6).
Figure 23.1 shows the AUD block diagram.
L bus I bus P bus
AUDMD
AUDRST
AUDCK
AUDSYNC
AUDATA3 to
AUDATA0
FIFO
PC output circuit
Address buffer
Data buffer
Mode control
Figure 23.1 Block Diagram of AUD
On-chip
memory
On-chip
peripheral
module
Rev. 3.00 Oct. 06, 2008 Page 926 of 1080
REJ09B0230-0300