SH7147 Datasheet, PDF (635/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.4.3 Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3
shows the relationship.
The synchronous serial communication unit transmits serial data from the SSO pin and receives
serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode)
(see figure 14.3 (1)). The synchronous serial communication unit transmits serial data from the
SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0
(standard, slave mode) (see figure 14.3 (2)).
The synchronous serial communication unit transmits and receives serial data from the SSO pin
regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see
figures 14.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The synchronous serial communication unit transmits serial data from the SSO pin and receives
serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal
clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 14.3 (5) and (6)).
Rev. 3.00 Oct. 06, 2008 Page 611 of 1080
REJ09B0230-0300